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<p class=MsoNormal><font size=2 face=Verdana><span style='font-size:10.0pt;
font-family:Verdana'>Hey all,<br>
<br>
The following positions will be available at an upcoming startup. The company
will be based in between Mass and Lebanon, and will offer competitive
compensation, incentive stock options, and more:</span></font></p>
<p class=MsoNormal><b><font size=2 face=Verdana><span style='font-size:10.0pt;
font-family:Verdana;font-weight:bold'> </span></font></b></p>
<p class=MsoNormal style='margin-left:36.0pt'><b><font size=2 face=Verdana><span
style='font-size:10.0pt;font-family:Verdana;font-weight:bold'>SR. Chip
Designer:</span></font></b></p>
<p class=MsoNormal style='margin-left:36.0pt'><font size=2 face=Verdana><span
style='font-size:10.0pt;font-family:Verdana'>Responsible for the design and
verification of an FPGA based transmission test device using xilinx
Virtex-IV with Rocket IO. Responsibilities include logic design, functional
verification, synthesis, and timing analysis and optimization --- The job
requires very good understanding of ASIC design flow including development of
RTL in Verilog, simulation, synthesis, P&R, and timing optimization.
Knowledge of system design and resources such as buses, bridges, and memory
subsystems and controllers is highly desired. Knowledge of signals and systems,
signal transmission is a plus. 5+ years of system and logic design
experience is required.</span></font></p>
<p class=MsoNormal style='margin-left:36.0pt'><font size=2 face=Verdana><span
style='font-size:10.0pt;font-family:Verdana'> </span></font></p>
<p class=MsoNormal style='margin-left:36.0pt'><b><font size=2 face=Verdana><span
style='font-size:10.0pt;font-family:Verdana;font-weight:bold'>Hardware
Designer:</span></font></b></p>
<p class=MsoNormal style='margin-left:36.0pt'><font size=2 face=Verdana><span
style='font-size:10.0pt;font-family:Verdana'>5 years minimum board level
hardware design experience in communications and networking area. Must be
proficient in Schematic capture (for Orcad or DxDesign tools), and symbol
creation. Proficient in PCB layout design process, including tasks like
floor-planning, pin escapes, routing rules constraints, full understanding of
PCB manufacturing and assembly requirements. A solid understanding of
circuit design, high speed signaling & transmission, system timing and clocking
techniques, managing noise and jitter budgets, signal integrity analysis, power
delivery design. Familiarity with high speed I/O such as CML, PECL, LVDS. High
speed logic design experience using Xilinx FPGA and CPLD
devices. Familiarity with high speed measurements techniques and equipment.</span></font></p>
<p class=MsoNormal><font size=2 face=Verdana><span style='font-size:10.0pt;
font-family:Verdana'><br>
<br>
Please circulate widely and feel free to contact me if you’re interested
or need more information.<br>
<br>
Thanks,<br>
L.</span></font></p>
<p class=MsoNormal><font size=2 face=Verdana><span style='font-size:10.0pt;
font-family:Verdana'> </span></font></p>
<p><font size=2 face=Verdana><span style='font-size:10.0pt;font-family:Verdana'>_____________________________________<br>
<strong><b><font face=Verdana><span style='font-family:Verdana'>Loai Naamani</span></font></b></strong><br>
PhD Candidate - Information Technology<br>
Massachusetts Institute of Technology (MIT)<br>
<br>
Phone: +1 (617) 452 5380<br>
Email: <a href="mailto:Loai@mit.edu">Loai@mit.edu</a><br>
URL: <a
href="http://www.loai-naamani.com/">www.Loai-Naamani.com</a><br>
</span></font></p>
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12.0pt'> </span></font></p>
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