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<b>For Immediate Release</b><br>
WEDNESDAY, SEP. 16, 2009<br>
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Contact: Jen Hirsch, MIT News Office<br>
E: jfhirsch@mit.edu, T: 617-253-1682<br>
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MIT team finds way to combine microprocessor materials<br>
--Produces faster, highly efficient chip<br>
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<font face="Arial"><b>** For a longer version of this story: </b></font><font face="Arial">http://web.mit.edu/newsoffice/2009/palacios-chip-091509.html<b> ***<br>
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Results</b>: An MIT team led by Tomás Palacios, assistant professor in the Department of Electrical Engineering and Computer Science, has succeeded in combining two semiconductor materials, silicon and gallium nitride, that have different and potentially complementary characteristics, into a single hybrid microchip. This is something researchers have been attempting to do for decades. <br>
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<b>Why it matters</b>: This advance could point to a way of overcoming fundamental barriers of size and speed facing today’s silicon chips. “We won’t be able to continue improving silicon by scaling it down for long,” Palacios says, so it’s crucial to find other approaches. Besides microprocessor chips, the new integrated technology can be used for other applications such as hybrid chips that combine lasers and electronic components on a single chip, and energy-harvesting devices that can harness the pressure and vibrations from the environment to produce enough power to run the silicon components. It could also lead to more efficient cell phone manufacturing, replacing four or five separate chips made from different semiconductor materials. “With this technology, you could potentially integrate all these functions on a single chip,” Palacios says.<br>
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<b>How they did it</b>: Instead of trying to grow the high-performance semiconductor material on top of a silicon chip as others have attempted, Palacios and his student Will Chung made the new hybrid chip by embedding a gallium nitride layer into the same type of silicon substrate that is used by the silicon electronics industry. This not only produces a faster chip, but one that is highly efficient. The chips can be manufactured using the standard technology currently used for commercial silicon chips.<br>
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<b>Next steps</b>: The new technique has been used to make chips that are about one square inch in size. Conventional chip manufacturing processes typically use larger wafers, 8 or 12 inches in diameter, so the research now is focused on scaling up the process. “We have several ideas in that direction,” Palacios says. “We are already discussing with several companies how to commercialize this technology and fabricate more complex circuits.” However, it could take a couple of years to get to the point where it could be commercialized, he says.<br>
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Source: </b>“Seamless On-Wafer Integration of Si(100) MOSFETs and GaN HEMTs” <br>
Jinwook W. Chung, Tomás Palacios, et al<br>
IEEE Electron Device Letters, October 2009<br>
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Funding:</b> Funding from DARPA Young Faculty Award, the MARCO Interconnect Focus Center and the MIT Deshpande Center. Fabrication was done at MIT’s Microsystems Technology Laboratories and Nano-Structures Laboratory.<br>
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<i>Written by David Chandler, MIT News Office</i>
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